A typical LCD panel comprises plural gate lines connected to a gate driver and plural data lines connected to a data driver (also referred as a source driver). For effectively reducing the number of data lines to reduce the fabricating cost, a LCD panel with a tri-gate pixel configuration has been disclosed. In the tri-gate pixel configuration, the sub-pixels R, G and B of each pixel are sequentially arranged along the data line. In such way, the number of gate drivers is tripled to constitute a complete frame. As known, a LCD panel integrating a gate driver on array (GOA) circuit may reduce the overall fabricating cost.
FIG. 1A is a schematic circuit diagram illustrating a conventional LCD panel, which is disclosed in US Patent Application No. US2007/0091044. The LCD panel has a tri-gate pixel configuration. As shown in FIG. 1A, the LCD panel comprises a data driver and a pixel array. The data driver comprises plural data driver integrated circuits 141, which are connected with m data lines D1˜Dm. The gate driver is connected with 3n gate lines G1˜G3n. The gate driver comprises a first gate driver integrated circuit 150L and a second gate driver integrated circuit 150R. The gate driver integrated circuit 150L is connected with the odd-numbered gate lines. The second gate driver integrated circuit 150R is connected with the even-numbered gate lines.
For example, the pixel PX11 comprises three sub-pixels, which are controlled by the gate pulses from a first gate line G1, a second gate line G2 and a third gate line G3, respectively. For enhancing the display quality and reducing the overall power consumption of the LCD panel, the data lines are driven by a column inversion driving method. As a result, the driving polarities of every two adjacent data lines are opposite at the same time. Generally, a common voltage Vcom is received by the LCD panel. The data line having a voltage value higher than the common voltage has a positive polarity (+). The data line having a voltage value lower than the common voltage has a negative polarity (−).
The way of arranging the sub-pixels of the LCD panel of FIG. 1A, however, may incur some drawbacks during the process of displaying some regular frames. For example, when the voltages of the data lines are simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state, the common voltage Vcom may be deviated from the original level because of a coupling effect. Under this circumstance, the voltage levels for writing to the sub-pixels are adversely affected, and thus the displaying quality of the frame is usually deteriorated.
FIG. 1B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 1A when bright/dark vertical fringes are displayed. The common voltage Vcom is 4 volts. The even-numbered data lines have the negative polarity. The odd-numbered data lines have the positive polarity. If the voltage value of the data line is equal to the common voltage Vcom, the sub-pixels corresponding to the data line are in the full-bright state. Whereas, if the voltage value of the data line is equal to 0V or 8V, the sub-pixels corresponding to the data line are in the full-dark state.
Obviously, in a case that the data lines of the LCD panel are driven by a column inversion driving method to display the bright/dark vertical fringes, the voltage of the even-numbered data lines (e.g. the second data line D2 and the fourth data line D4) are alternately changed between 4V and 0V in response to the gate pulses (G1˜G12) of the gate lines. Similarly, the voltage of the odd-numbered data lines (e.g. the third data line D3 and the fifth data line D5) are alternately changed between 8V and 4V in response to the gate pulses (G1˜G12) of the gate lines. In such way, the bright/dark vertical fringes are shown on the frame.
As can be seen from FIG. 1B, when the voltages of the data lines are simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state (i.e. in the transition condition), the common voltage Vcom may be deviated from the original level because of a coupling effect. Under this circumstance, the voltage levels for writing to the sub-pixels are adversely affected, and thus the displaying quality of the frame is usually deteriorated.
Please refer to FIGS. 2A and 2B. FIG. 2A is a schematic circuit diagram illustrating a gate driver according to the prior art. FIG. 2B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver of FIG. 2A. The gate driver 410 comprises plural shift register units 411˜418. According to four clock signals C1˜C4, the shift register units 411˜418 generate four gate pulses g1˜g4 to the gate line G1˜G4 of the visible zone 420, respectively. The operations of the gate driver 410 will be illustrated in more details as follows.
In response to a start signal ST, the first shift register unit 411 and the second shift register unit 412 issue the first gate pulse g1 and the second gate pulse g2 to the first gate line G1 and the second gate line G2 according to the first clock signal C1 and the second clock signal C2, respectively. The third shift register unit 413 is informed by the first shift register unit 411 to issue the third gate pulse g3 to the third second gate line G3 according to the third clock signal C3. The fourth shift register unit 414 is informed by the second shift register unit 412 to issue the fourth gate pulse g4 to the fourth gate line G4 according to the fourth clock signal C4. The operations of the shift register units 415˜418 and the successive shift register units are similar to those illustrated above, and are not redundantly described herein. The four clock signals C1˜C4 have the same frequency. In addition, the phase difference between any two adjacent clock signals of the four clock signals C1˜C4 is 90 degrees.
Please refer to FIG. 2B again. Take the first gate pulse g1 for example. The first half of the first gate pulse g1 is a pre-charge time t1, and the last half of the first gate pulse g1 is a data writing time t2. Similarly, each of the pulse signals includes a pre-charge time and a data writing time. By this operating method, the gate pulses outputted from every two gate lines neighboring the sub-pixel may be overlapped with each other for a data writing time t2. In other words, during the period of writing this data, the voltage of the sub-pixel is adversely affected by the adjacent gate line through the parasitic capacitance between the sub-pixel and the gate line. Under this circumstance, the displaying quality of the frame is deteriorated.